1. Field of the Invention
This invention relates to a semiconductor substrate comprising a semiconductor layer arranged on a supporting base member and also to a method of manufacturing such a semiconductor substrate.
2. Related Background Art
SOI (semiconductor on insulator) substrates having an SOI structure obtained by forming a single crystal semiconductor layer on an insulation layer are well known. Devices comprising an SOI substrate provide a number of advantages over ordinary Si substrates, including the following:
(1) easy dielectric separation and adaptability to an enhanced degree of integration;
(2) excellent radiation resistance;
(3) small stray capacitance and potential for high speed device operation;
(4) no need of well-forming process;
(5) reliable latch-up prevention; and
(6) capability of reducing the film thickness and forming fully depleted type field effect transistors.
Because of the advantages of the SOI structure including the above, massive efforts have been paid for developing various methods of manufacturing substrates having an SOI structure in the last decades.
The SOI technology can go back to the days of the SOS (silicon on sapphire) technology of forming an Si layer on a single crystal sapphire substrate by means of hetero-epitaxial growth, using a CVD (chemical vapor phase growth) method. While the SOS technology is appreciated by many as one of the most matured technologies, it has not been commercialized remarkably because it is accompanied by a number of drawbacks including the generation of a large number of crystal defects due to lattice misalignment along the interface of the Si layer and the underlying sapphire substrate, the existence of aluminum mixed into the Si layer from the sapphire substrate originally containing it, a high cost of the substrate and a poor adaptability to the trend toward larger substrates.
The SIMOX (separation by ion implanted oxygen) technology followed the SOS technology. There have been various research efforts paid in the field of the SIMOX technology to reduce the crystal defects and the manufacturing cost. The methods known to date other than the SIMOX technology include a method of bonding a pair of wafers with an oxide film interposed therebetween and polishing or etching one of the wafers to leave a thin single crystal Si layer on the oxide film, a method of implanting hydrogen ions from the surface of an Si substrate carrying thereon an oxide film to a predetermined depth, bonding the substrate to another substrate and then peeling off the latter substrate with a thin single crystal Si layer left on the oxide film typically by means of heat treatment.
With the above method of manufacturing an SOI semiconductor substrate by bonding a pair of silicon wafers to each other with an insulation film interposed therebetween and thinning one of the substrates to produce a thin film or an Si layer on the insulation film, the strength of bonding the silicon substrates can be reduced and even nullified in the peripheral area as it is adversely affected typically by the operation of beveling the substrates.
Then, SOI wafers under such conditions can become chipped in areas where the bonding strength is not sufficient and the surfaces of the wafers can become damaged, if partly, by Si debris in the course of manufacturing semiconductor devices to reduce the yield of manufacturing high quality semiconductor devices.
To cope with this problem, techniques have been developed for removing silicon layers in areas showing a weak bonding strength. For instance, Japanese Patent No. 2658135 discloses a technique for preventing a chipping phenomenon from occurring in a semiconductor substrate comprising a semiconductor layer arranged on a support member by mechanically grinding the outer peripheral edge of the support member by means of a wheel having a electrodeposition surface of diamond. However, highly integrated high-density semiconductor devices require further preventive measures for preventing the appearance of fine debris.
FIGS. 13A through 13E of the accompanying drawings schematically illustrate a silicon removing process proposed by the inventors of the present invention. FIG. 13A shows an SOI substrate 5 prepared by bonding and etching-back operations and comprising an insulation film 2 and a thinned silicon layer 3 that are formed on a support member 1. An outer peripheral portion of the silicon layer 3 of the SOI substrate 5 has to be removed because the bonding strength is weak in that portion. The use of photolithography is the most popular technique for removing a silicon layer in the semiconductor technology. With such a technique, photoresist is applied to the surface of the SOI substrate and the applied photoresist is exposed to light so that only the photoresist on the portion of the silicon layer 3 to be removed may be removed. Thus, a photoresist mask as shown in FIG. 13B is produced. Then, as shown in FIG. 13C, the exposed extreme end portion of the silicon layer 3 showing only a weak bonding strength is removed, using the remaining photoresist as mask. Thereafter, a corresponding extreme end portion of the insulation film 2 located under the silicon layer 3 is removed. A wet etching technique using hydrofluoric acid as etchant is popularly employed for removing part of the insulation film 2 because it does not damage the underlying support member 1. Since the wet etching process proceeds isotropically, the insulation film 2 is also etched in an upper portion of its outer periphery located under the silicon layer 3 to produce an undercut as shown in FIG. 13D. The silicon removing process is completed when the photoresist is removed (FIG. 13E).
Thus, a peripheral portion of the silicon layer 3 showing a weak bonding strength is removed.
Note that, in the above illustration of an SOI substrate 5 prepared by bonding and etching-back operations, the support member 1 and the insulation film 2 are bonded together along their interface so that a portion of the insulation film 2 located directly under the removed extreme end portion of the silicon layer also has to be removed.
However, once an extreme end portion of the silicon layer 3 showing a weak bonding strength is removed, the remaining silicon layer 3 can become etched laterally when a corresponding extreme end portion of the insulation film 2 located under the silicon layer 3 is removed to produce an undercut there so that the outer peripheral end portion of the silicon layer located on the undercut will become overhung and not bonded at all. Then, the overhanging outer peripheral end portion of the silicon layer 3 can eventually give rise to a chipping phenomenon and produce debris.
Thus, it is the object of the present invention to provide a semiconductor substrate that does not produce a chipping phenomenon, giving rise to debris from the outer peripheral extremity of the semiconductor layer and also a method of manufacturing such a semiconductor substrate.
According to an aspect of the invention, the above object is achieved by providing a semiconductor substrate comprising a support member, an insulation layer arranged on the support member and a semiconductor layer arranged on the insulation layer, characterized in that the outer peripheral extremity of said semiconductor layer is located inside the outer peripheral extremity of said support member and the outer peripheral extremity of said insulation layer is located between the outer peripheral extremity of said semiconductor layer and that of said support member so that the outer peripheral portion of the semiconductor substrate including said insulation layer and said semiconductor layer shows a stepped profile.
According to another aspect of the invention, there is provided a method of manufacturing a semiconductor substrate having a support member, an insulation layer arranged on the support member and a semiconductor layer arranged on the insulation layer, characterized by comprising steps of removing an extreme portion from said insulation layer and also an extreme portion from said semiconductor layer so as to make both the outer peripheral extremity of said insulation layer and that of said semiconductor layer to be located inside the outer peripheral extremity of said support member and removing an extreme portion from said semiconductor layer so as to make the outer peripheral extremity of said semiconductor layer to be located inside the outer peripheral extremity of said insulation layer.
A semiconductor substrate having a configuration as described above can hardly produce an overhanging profile for the outer peripheral extremity and consequently reduce the possibility of occurrence of a chipping phenomenon to a great extent if the insulation layer is laterally etched in the manufacturing process.
Additionally, since the portion of the semiconductor substrate that shows a weak bonding strength is removed, the production of debris from the peripheral area of the substrate will be minimized.